library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--library MACHXO3;
--use MACHXO3.all;

entity testCC2510 is
	port(clkin: in std_logic;
		reset: in std_logic;
		SW4: in std_logic;
		LED: out std_logic_vector(7 downto 0);
		com: out std_logic;
		D2_out: out std_logic_vector(6 downto 0);
		D1_out: out std_logic_vector(6 downto 0);
		D0_out: out std_logic_vector(6 downto 0);
		DP1_out: out std_logic;
		DP2_out: out std_logic;
		LED_out: out std_logic_vector(7 downto 0));
		
--	define the pin connections
	attribute loc:string;
	attribute loc of clkin: signal is "C8";
	attribute loc of D0_out: signal is "R13,T14,T12,R11,T11,M11,N10";
	attribute loc of D1_out: signal is "R10,P10,T10,R9,T9,N9,M8";
	attribute loc of D2_out: signal is "M6,L8,T8,P8,R7,R8,T7";
	attribute loc of com: signal is "P7";
	attribute loc of reset: signal is "D2";--was K1
	attribute loc of SW4: signal is "N1";
	attribute loc of DP1_out: signal is "P9";
	attribute loc of DP2_out: signal is "P11";
	attribute loc of LED_out: signal is "F3,D3,G3,C2,F5,E3,B1,C1";
end;


architecture arch_testCC2510 of testCC2510 is
	
	component SevenSeg
		port(LEDin: in integer;
			SevSegout: out std_logic_vector);
	end component;
	
	signal clkreg : std_logic_vector(31 downto 0);
	signal c_clk: std_logic;
	signal dig2: std_logic_vector(6 downto 0):="1111111";
	signal dig1: std_logic_vector(6 downto 0);
	signal dig0: std_logic_vector(6 downto 0);
	signal DP1: std_logic:='1';
	signal DP2: std_logic:='1';
	signal count0: integer range 0 to 9;
	signal count1: integer range 0 to 9;
	signal oscpin: std_logic;


begin

	clk1:process(clkin)
		begin
		 if (clkin'event and clkin = '1') then			
			clkreg <= clkreg+X"00000001";
		end if;
		
		c_clk <= clkreg(22);
		oscpin <= clkreg(15);
	
	end process clk1;
	
	lcdmod:process(oscpin)
		begin
		 if (oscpin='1') then
			D2_out<=dig2;
			D1_out<=dig1;
			D0_out<=dig0;
			DP1_out<=DP1;
			DP2_out<=DP2;
		 else
			D2_out<= not dig2;
			D1_out<= not dig1;
			D0_out<= not dig0;
			DP1_out<= not DP1;
			DP2_out<= not DP2;
		 end if;
			com<=oscpin;
			
	end process;
	
	DD0:SevenSeg port map(count0,dig0);
	DD1:SevenSeg port map(count1,dig1);
	

	
	p_counter: process
	begin
		wait until rising_edge(c_clk);
		
		if (SW4='1') then
		if (((count1=9) and (count0=9)) or reset='0') then
			count1<=0;
			count0<=0;
		elsif(count0=9) then
			count1<=count1+1;
			count0<=0;
		else
			count0<=count0+1;
		end if;
		end if;
		
--			***place Practical No 2 code here***

	end process p_counter;
	
	
		LED_out <= "00000000";

end arch_testCC2510;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity SevenSeg is
	port(LEDin: integer range 0 to 9;
		SevSegout: out std_logic_vector(6 downto 0));
end;
architecture SevenSeg_arch of SevenSeg is
begin
	process(LEDin)
	begin
		Lab0:case LEDin is
			when 0=>SevSegout<="0000001";
			when 1=>SevSegout<="1001111";
			when 2=>SevSegout<="0010010";
			when 3=>SevSegout<="0000110";
			when 4=>SevSegout<="1001100";
			when 5=>SevSegout<="0100100";
			when 6=>SevSegout<="0100000";
			when 7=>SevSegout<="0001111";
			when 8=>SevSegout<="0000000";
			when 9=>SevSegout<="0000100";
		end case Lab0;
	end process;
end SevenSeg_arch;